In many new integrated circuits leakage of transistors is becoming an increasing contributor to total power consumption of the circuits. Leakage of transistors is the drawing of unnecessary current from the supply during operation of the circuits or when the circuits are in standby mode. There are several sources of leakage including sub-threshold leakage, leakage due to gate-induced barrier lowering, gate-tunneling leakage, etc.
Leakage of transistors within cells may cause a number of problems, including, for example, contributing to improper functioning of the circuit or yield loss. Thus, it is desired to reduce the leakage of cells. Conventionally there are two methods to create low-leakage versions of cells. In one method, each transistor in a cell may be upsized by extending a gate length of the transistor. In another method, one or more transistors in the cell may have a higher-threshold voltage compared to a nominal threshold voltage for a process technology with which the cell is being utilized. These methods may, however, cause significant performance penalties such as higher delays, increased size of the cell or an increase in the switching power of the cell.